The use of ESD protection circuitry for protecting an integrated circuit (IC) device from damage caused by the discharge of static electricity and/or other transient pulses (e.g., load dump) through the device is well known. An ESD event, which may include any large voltage and/or current transient pulse, may not necessarily cause immediate (i.e., catastrophic) failure of the device, but may damage only a portion of the device and/or cause a latent defect that can significantly shorten the operating life or negatively impact the reliability of the device.
Various methodologies have been proposed for protecting a circuit from ESD, particularly between two or more isolated power pins in the IC device. FIGS. 1A and 1B illustrate examples of two conventional protection schemes for providing ESD protection between two isolated power pins PWR1 and PWR2. Each of these approaches is designed to provide an ESD discharge path between a given one of the power pins and a ground pin GND. With reference to FIG. 1A, ESD protection circuit 100 relies on ESD clamps 102 and 104, and diodes 106 and 108, connected between power pins PWR1 and PWR2, respectively, and ground. The ESD clamps 102, 104 generally include a large metal-oxide-semiconductor (MOS) transistor device (not shown). One problem with this approach, however, is that the voltage drop across the path between power pin PWR1 or PWR2 and ground may be too high, such that a breakdown of the MOS transistor device in a corresponding ESD clamp 102, 104 occurs, rendering the ESD protection circuit 100 essentially inoperable.
The ESD protection circuit 150 shown in FIG. 1B is similar to the circuit 100 shown in FIG. 1A in that circuit 150 includes ESD clamps 102 and 104, and diodes 106 and 108, connected between power pins PWR1 and PWR2, respectively, and ground pin GND. Additionally, circuit 150 includes two diodes 110 and 112 connected between the power pins PWR1 and PWR2 in a back-to-back configuration. Specifically, an anode of a first diode 110 is connected to PWR1 and a cathode of diode 110 is connected to PWR2, while an anode of diode 112 is connected to PWR2 and a cathode of diode 112 is connected to PWR1. This ESD protection approach, however, requires that the respective supply voltages applied to power pins PWR1 and PWR2 must substantially track one another, and therefore must be of the same magnitudes relative to one another. If the two voltages differ from one another by more than about 0.7 volt, the lower potential supply will be powered by the higher potential supply through a forward-biased diode (e.g., diode 110 or diode 112). Furthermore, although relying on a parasitic bipolar NPN snapback type transistor associated with the MOS device for clamping may have some limited merit, the snapback voltage is typically too high and/or uncontrollable; and thus undesirable.
Accordingly, there exists a need for an improved ESD protection circuit for protecting an IC device from ESD, particularly between two or more isolated power pins associated with the IC device, that does not suffer from one or more of the problems exhibited by conventional ESD protection circuitry.